Tuesday, June 21, 2011

Domino Calculator - Improving the Half Adder

This post is an improvement to the domino half adder discussed in the last post, I suggest you read that first before reading this one.

In the first half adder implementation there was a large amount of dominoes going in many directions and required the use of a bridge to get the logical value of B over to do a logical AND operation.  Since I plan on implementing this in the future the bridge was a bad idea.

When observing the circuit notice that the line from S and the line from Bit A can be used side by side with no bridge nessessary. So lets look a the truth table again and see if we can find another way to find the Carry using Bit A and the Sum.

Bit ABit BSumCarry
0000
0110
1010
1101

Notice that the only time Carry is 1 is when B = 1 and S = 0.  So the logical operation to find the Carry from B and S is: C = B AND ~S (Where ~ is logical NOT). Which creates this circuit diagram.

The circle on the AND gate is the symbol for logical NOT operation.
The downside to this circuit design is that the XOR operation and the AND operation are not performed in parallel, the AND operation must wait for the XOR operation to complete.  However for dominoes this is okay because it eliminates the need to cross over a line.

To implement this new logical circuit we are going to use the same XOR gate implementation, grab the logical value of S(Sum), negate it, and then perform a logical AND operation using the value of bit A. The last iteration of the half adder contained a segment that did a logical AND operation between two bits which looked like this:


Remember that the black dominoes are always a value of 1.  I labeled them V because it is similar to the voltage in a electronic circuit.  This AND implementation takes the logical value from one of the bits and negates it.  Now the AND gate we are trying to build needs one of the inputs negated, so the action of performing the logical NOT is unnecessary.  This leaves us with this implementation:


The time delay is so that the result from the XOR operation can finish before the value of A gets to the gate.  Because the value of S knocks out a block it needs to be done before the value from A gets there.

Next I implement a full adder then a ripple!

2 comments:

  1. Madison, I have to be honest, all of this was over my head. BUT, i wanted you to know that i miss you and that I think you should change your blog to a tumblr so that me, you, farris, and court, etc... can all follow each other. I lub you,

    marie

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  2. Hey, great post. Very clever scheme making half-adder without wire crossing. The circuit diagram is "right" but the output for the Carry ought to be blue, ie True signal for your example.

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